1 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus august 2002 2002 integrated device technology, inc. dsc 5828/3 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? ref input is 5v tolerant ? 4 pairs of programmable skew outputs ? low skew: 200ps same pair, 250ps all outputs ? selectable positive or negative edge synchronization: excellent for dsp applications ? synchronous output enable ? input frequency: 17.5mhz to 133mhz ? output frequency: 17.5mhz to 133mhz ? 2x, 4x, 1/2, and 1/4 outputs (of vco frequency) ? 3-level inputs for skew control ? pll bypass for dc testing ? external feedback, internal loop filter ? 12ma balanced drive outputs ? low jitter: <200ps cycle-to-cycle ? available in plcc and tqfp packages functional block diagram soe 1q 0 skew select 1q 1 1f1:0 3 3 2q 0 skew select 2q 1 2f1:0 3 ref pll fb 3 3q 0 skew select 3q 1 3f1:0 3 3 4q 0 4q 1 skew select 4f1:0 3 3 pe test idt5v994 3.3v programmable skew pll clock driver turboclock? plus description the idt5v994 is a high fanout 3.3v pll based clock driver intended for high performance computing and data-communications applications. a key feature of the programmable skew is the ability of outputs to lead or lag the ref input signal. the idt5v994 has eight programmable skew outputs in four banks of 2. skew is controlled by 3-level input signals that may be hard- wired to appropriate high-mid-low levels. when the soe pin is held low, all the outputs are synchronously enabled. however, if soe is held high, all the outputs except 3q0 and 3q1 are synchronously disabled. furthermore, when the pe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when pe is held low, all the outputs are synchronized with the negative edge of ref. the idt5v994 has lvttl outputs with 12ma balanced drive outputs.
2 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus pin configurations note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit v ddq , v dd supply voltage to ground?0.5 to +4.6 v v i dc input voltage ?0.5 to v dd +0.5 v ref input voltage ?0.5 to +5.5 v maximum power dissipation, t a = 85c 0.8 w t stg storage temperature range ?65 to +150 c note: 1. capacitance applies to all inputs except test, fs, and nf [1:0] . capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 5 7 pf tqfp top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f1 4f0 4f1 pe v ddq 4q1 4q0 gnd gnd 2f0 soe 1f1 1f0 1q0 1q1 gnd gnd 4 3 2 1 32 31 30 14 15 16 17 18 19 20 3 f 0 r e f g n d t e s t 2 f 1 3 q 1 3 q 0 f b 2 q 1 2 q 0 v d d q v d d q v ddq v d d v d d programmable skew output skew with respect to the ref input is adjustable to compensate for pcb trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. skew is selectable as a multiple of a time unit t u which is of the order of a nanosecond (see pll programmable skew range and resolution table). there are nine skew configurations available for each output pair. these configurations are chosen by the nf 1:0 control pins. in order to minimize the number of control pins, 3-level inputs (high-mid-low) are used, they are intended for but not restricted to hard-wiring. undriven 3-level inputs default to the mid level. where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. the control summary table shows how to select specific skew taps by using the nf 1:0 control pins. plcc top view 32 3 f 0 31 v d d 30 v d d 29 r e f 26 2 f 1 28 27 g n d t e s t 25 2 f 0 9 3 q 1 10 3 q 0 11 v d d q 12 f b 15 2 q 0 13 14 2 q 1 v d d q 16 g n d 1 2 3 4 5 6 7 8 3f1 4f0 4f1 pe v ddq 4q1 4q0 gnd 24 23 22 21 20 19 18 17 soe 1f1 1f0 1q0 1q1 gnd v ddq gnd
3 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus note: 1. when test = mid and soe = high, pll remains active with nf[ 1:0 ] = ll functioning as an output disable control for individual output banks. skew selections remain in effect unless nf[ 1:0 ] = ll. pin description pin name type description ref i n reference clock input fb i n feedback input test (1) i n when mid or high, disables pll (except for conditions of note 1). ref goes to all outputs. skew selections (see control sum mary table) remain in effect. set low for normal operation. soe (1) i n synchronous output enable. when high, it stops clock outputs (except 3q 0 and 3q 1 ) in a low state - 3q 0 and 3q 1 may be used as the feedback signal to maintain phase lock. when test is held at mid level and soe is high, the nf[ 1:0 ] pins act as output disable controls for individual banks when nf[ 1:0 ] = ll. set soe low for normal operation. pe i n selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge o f the reference clock. nf [1:0] i n 3-level inputs for selecting 1 of 9 skew taps or frequency functions nq [1:0] out four banks of two outputs with programmable skew v ddq pwr power supply for output buffers v dd pwr power supply for phase locked loop and other internal circuitry gnd pwr ground external feedback by providing external feedback, the idt5v994 gives users flexibility with regard to skew adjustment. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. notes: 1. the vco frequency always appears at 1q 1:0 , 2q 1:0 , and the higher outputs when they are operated in their undivided modes. the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for frequency multiplication by using a divided output as the fb input. using the nf[ 1:0 ] inputs allows a different method for frequency multiplication (see control summary table for feedback signals). 2. skew adjustment range assumes that a zero skew output is used for feedback. if a skewed q output is used for feedback, then a djustment range will be greater. for example if a 4t u skewed output is used for feedback, all other outputs will be skewed ?4t u in addition to whatever skew value is programmed for those outputs. ?max adjustment? range applies to output pairs 3 and 4 where 6t u skew adjustment is possible and at the lowest f nom value. comments timing unit calculation (t u ) 1/(16 x f nom ) vco frequency range (f nom ) (1,2) 70 to 133mhz skew adjustment range (2) max adjustment: 5.36ns ns 135 phase degrees 37.5% % of cycle time example 1, f nom = 80mhz t u = 0.78ns example 2, f nom = 100mhz t u = 0.63ns example 3, f nom = 133mhz t u = 0.47ns programmable skew range and resolution table
4 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus control summary table for feedback signals nf1:0 skew (pair #1, #2) skew (pair #3) skew (pair #4) ll (1) ?4t u divide by 2 divide by 2 lm ?3t u ?6t u ?6t u lh ?2t u ?4t u ?4t u ml ?1t u ?2t u ?2t u m m zero skew zero skew zero skew mh 1t u 2t u 2t u hl 2t u 4t u 4t u hm 3t u 6t u 6t u hh 4t u divide by 4 inverted (2) notes: 1. ll disables outputs if test = mid and soe = high. 2. when pair #4 is set to hh (inverted), soe disables pair #4 high when pe = high, soe disables pair #4 low when pe = low. recommended operating range symbol description min. typ. max. unit v dd /v ddq power supply voltage 3 3.3 3.6 v t a ambient operating temperature -40 +25 +85 c dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) 2 ? v v il input low voltage guaranteed logic low (ref, fb inputs only) ? 0.8 v v ihh input high voltage (1) 3-level inputs only v dd ? 0.6 ? v v imm input mid voltage (1) 3-level inputs only v dd /2 ? 0.3 v dd /2+0.3 v v ill input low voltage (1) 3-level inputs only ? 0.6 v i in input leakage current v in = v dd or gnd ? 5+5a (ref, fb inputs only) v dd = max. v in = v dd high level ? +200 i 3 3-level input dc current v in = v dd /2 mid level ? 50 +50 a (test, fs, nf [1:0] , ds [1:0] )v in = gnd low level ? 200 ? i pu input pull-up current (pe) v dd = max., v in = gnd ? 100 ? a i pd input pull-down current ( soe )v dd = max., v in = v dd ? +100 a v oh output high voltage v ddq = min., i oh = ? 12ma 2.4 ? v v ol output low voltage v ddq = min., i ol = 12ma ? 0.4 v note: 1. these inputs are normally wired to v dd , gnd, or unconnected. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved.
5 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus power supply characteristics symbol parameter test conditions (1) typ. max. unit i ddq quiescent power supply current v dd = max., test = mid, ref = low, 8 25 ma pe = low, soe = low all outputs unloaded ? i dd power supply current per input high v dd = max., v in = 3v, 1 30 a i ddd dynamic power supply current per output v dd /v ddq = max., c l = 0pf 55 90 a/mhz v dd /v ddq = 3.3v , f ref = 83mhz, c l = 160pf (1) 31 ? i tot total power supply current v dd /v ddq = 3.3v , f ref = 100mhz, c l = 160pf (1) 34 ? m a v dd /v ddq = 3.3v , f ref = 133mhz, c l = 160pf (1) 39 ? note: 1. for eight outputs, each loaded with 20pf. notes: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies. 2. the minimum reference clock input frequency is 70mhz if q/2 or q/4 are not used as feedback input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall tim es, 0.8v to 2v ? 10 ns/v t pwc input clock pulse, high or low 2 ? ns d h input duty cycle 10 90 % f ref reference clock input frequency (2) 17.5 133 m h z
6 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus switching characteristics over operating range symbol parameter min. typ. max. unit f nom vco frequency range see programmable skew range and resolution table t rpwh ref pulse width high (1) 2??ns t rpwl ref pulse width low (1) 2??ns t u programmable skew time unit see control summary table t skewpr zero output matched-pair skew (xq 0 , xq 1 ) (2,3) ? 0.05 0.2 ns t skew0 zero output skew (all outputs) (4) ? 0.1 0.25 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) (5) ? 0.25 0.5 ns t skew2 output skew (rise-fall, nominal-inverted, divided-divided) (5) ? 0.3 1.2 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) (5) ? 0.25 0.5 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) (2) ? 0.5 0.9 ns t dev device-to-device skew (2,6) ? ? 0.75 ns t ( ) ref input to fb static phase offset) (7) ? 0.25 0 0.25 ns t odcv output duty cycle variation from 50% ? 1.2 0 1.2 ns t pwh output high time deviation from 50% (8) ??2ns t pwl output low time deviation from 50% (9) ? ? 2.5 ns t orise output rise time 0.15 1 1.8 ns t ofall output fall time 0.15 1 1.8 ns t lock pll lock time (10) ? ? 0.5 ms t jr cycle-to-cycle output jitter (peak-to-peak) ? ? 200 ps notes: 1. refer to input timing requirements table for more detail. 2. skew is the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with the specified load. 3. t skewpr is the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 4. t sk(0) is the skew between outputs when they are selected for 0t u . 5. there are 3 classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide- by-4 mode). 6. t dev is the output-to-output skew between any two devices operating under the same conditions (v ddq , v dd , ambient temperature, air flow, etc.) 7. t is measured with ref input rise and fall times (from 0.8v to 2v) of 1ns. 8. measured at 2v. 9. measured at 0.8v. 10. t lock is the time that is required before synchronization is achieved. this specification is valid only after v dd /v ddq is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t is within specified limits.
7 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus 2.0v t pwl t pwh t orise t ofall 0.8v 1ns 1ns 2.0v 0.8v 3.0v 0v v th = 1.5v 150 ? v ddq output 150 ? 20pf ac test loads and waveforms lvttl input test waveform lvttl output waveform
8 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus ref fb q other q inverted q ref divided by 2 ref divided by 4 t ref t skew2 t skew3, 4 t skew1, 3, 4 t skew2, 4 t skew3, 4 t skew3, 4 t skew2 t skewpr t skew0, 1 t jr t odcv t odcv t rpwh t rpwl t skewpr t skew0, 1 t ( ) ac timing diagram notes: pe: the ac timing diagram applies to pe=v dd . for pe=gnd, the negative edge of fb aligns with the negative edge of ref, divided outputs change on the negative edge of ref, and the positive edges of the divide-by-2 and the divide-by-4 signals align. skew: the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 20pf and terminated with 75 ? to v ddq /2. t skewpr : the skew between a pair of outputs (xq 0 and xq 1 ) when all eight outputs are selected for 0t u . t skew0 : the skew between outputs when they are selected for 0t u . t dev : the output-to-output skew between any two devices operating under the same conditions (v ddq , v dd , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. t pwh is measured at 2v. t pwl is measured at 0.8v. t orise and t ofall are measured between 0.8v and 2v. t lock : the time that is required before synchronization is achieved. this specification is valid only after v dd /v ddq is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
9 industrial temperature range idt5v994 3.3v programmable skew pll clock driver turboclock plus ordering information idt xxxxx xx package device type 5v994 3.3v programmable skew pll clock driver turboclock plus 32-pin plcc 32-pin tqfp ji pfi package x -40c to +85c (industrial) i data sheet document history 1/21/02 pages 1, 2, 4 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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